FPGA-based tracking system for GNSS receivers

Abstract

This report presents the design and simulation of code and carrier tracking system for a GNSS receiver. The GNSS receiver processes the signal sent by satellites in space. These signal contain carrier wave signal, ranging code and navigation data in encrypted form. To demodulate the navigation data, the processing block should accurately track the phase of incoming code and the frequency of incoming carrier wave signal. In code tracking loop, a DLL is used where three replicas of incoming PRN code namely early PRN, prompt PRN and late PRN are generated and correlated with the incoming signal. The result of these correlators is a numerical value that determines how much the specific code replica correlates with the incoming PRN. Based on correlation value, a code loop discriminator decides in which direction the phase of the PRN code is to be shifted. Then a perfectly aligned PRN code is generated by the local code generator. In carrier tracking loop, a PLL is used where a local carrier wave signal is multiplied with the incoming signal to wipe off carrier signal and PRN code of the incoming signal. The output after multiplication is sent to the carrier loop discriminator to determine the carrier phase error. This error is filtered out using a carrier loop filter. Then the output from the filter is used as feedback to a NCO that generates a perfectly aligned carrier wave signal. The other half of this report deals with the VHDL programming of the tracking subsystems that can be synthesized in a FPGA kit. It should be noted that all subsystems of a tracking block cannot be hardware synthesized. A VHDL program and a testbench program for the subsystem that can be hardware synthesized is coded and tested in ISIM. Finally, a design for FPGA-based tracking system for GNSS receivers is proposed